1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods for etching openings in intermetallic insulating layers and a semiconductor device with a thin barrier layer and well-defined contact openings.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In the fabrication of semiconductor devices, numerous conductive device regions such as transistors, capacitors, and diodes may be formed on or above a semiconductor substrate. For example, a typical metal oxide semiconductor (MOS) transistor such as a NMOS or PMOS transistor generally includes a gate electrode formed above a substrate separated by a relatively thin gate dielectric. Conductive regions and layers of the device may be isolated from one another by an interlevel dielectric. At various stages in the fabrication of semiconductor devices, it may be necessary to form openings in an interlevel dielectric layer to allow contact to underlying regions or layers. Generally, an opening through a dielectric layer exposing a diffusion region or an opening through a dielectric layer between polysilicon and a first metal layer is called a xe2x80x9ccontact openingxe2x80x9d or a xe2x80x9ccontact hole.xe2x80x9d An opening in other dielectric layers such as an opening through an interlevel dielectric layer is referred to as a xe2x80x9cvia.xe2x80x9d For purposes of this disclosure, henceforth xe2x80x9ccontact openingxe2x80x9d may be used to refer to a contact opening and/or a via. A contact opening may expose a diffusion region within a silicon substrate such as a source or drain, or may expose some other layer or structure such as an underlying metallization layer, a local interconnect layer, or a gate structure. Conductive contact structures may be formed within the contact opening, and interconnects may overlie the contact structures and may connect neighboring contact structures.
To form such a contact opening, a masking layer having openings therethrough may be formed over the dielectric layer. In most modern processes, a dry etch may then be performed in which the wafer may be exposed to a plasma. The plasma may be formed by flowing one or more gases such as one or more halocarbons and/or one or more other halogenated compounds such as CF4, CHF3,C4F8, C5F8, C4F6 (Freon 23), SF6, and NF3. In addition, gases such as O2, Ar, and N2 may also be added to the gas flow. After the opening has been formed thereby exposing a portion of the region or layer to be contacted, the opening may be cleaned with a sputter etch such as a radio-frequency sputter etch. The sputter etch may be used to remove small amounts of material which may form on sidewalls or on a bottom surface of the contact opening during the dry etch process. The opening may then be filled with a conductive material so that electrical contact can be made with the underlying region or layer.
There are, however, several disadvantages to conventional methods for forming contact structures. For example, a contact opening may be etched through a dielectric layer to an underlying layer, such as a semiconductor substrate or metal interconnect layer. In this manner, an underlying layer may be exposed to the etch chemistry used to etch the dielectric. Unfortunately, an undesirable compound may be formed on the upper surface of the underlying layer when the underlying layer is exposed to the etch chemistry. For example, exposing an underlying aluminum layer to an etch chemistry which includes a fluorinated hydrocarbon may cause formation of aluminum fluoride on the upper surface of the underlying layer. Other underlying layers may also react with fluorinated hydrocarbons of an etch chemistry to form undesirable compounds. Such compounds may often be very difficult, if not impossible, to remove by conventional methods. In addition, attempts to remove such compounds may adversely affect the operation or structure of the device if, for example, damage to other dielectric or conductive features of the device is caused during removal of these compounds. Furthermore, if such compounds remain in an etched contact opening, the resistance of a contact structure formed in the opening may be adversely increased thereby causing device malfunction.
To etch a contact opening without destroying an underlying layer as described above, a barrier layer may be formed between the underlying layer and the dielectric layer. A barrier layer material may be selected such that the barrier layer does not react with the etch chemistry to form the undesirable compounds described above. A thickness of the barrier layer may depend on the etch rate of the etch chemistry. For example, depending on the rate at which the barrier layer is removed by the etch chemistry, a thickness of the barrier layer may be selected such that the barrier layer is not completely removed during the etch process. Therefore, a thickness of the barrier layer may be selected such that etching may be terminated before the underlying layer is exposed to the etch chemistry. In this manner, a contact opening may be formed through the dielectric layer without destroying the underlying layer. There are, however, several disadvantages to using such a barrier layer for forming a contact structure. For example, processing time for forming such a barrier layer may be heavily dependent upon the thickness of the barrier layer required to protect the underlying layer. In addition, due to the etch rate of typical barrier layer materials using conventional etch chemistries, the thickness of the barrier layer required to protect an underlying layer may be approximately 500 angstroms to approximately 1000 angstroms. Therefore, forming such a barrier layer may increase overall processing time, thereby reducing overall throughput and efficiency of semiconductor device manufacturing processes. Furthermore, overall cost of a semiconductor device may increase due to the expensive nature of barrier layer materials.
Although protecting the underlying layer during the process of etching a contact opening is important, forming contact openings of uniform critical uniformity across a wafer is also important. xe2x80x9cCritical dimensionxe2x80x9d, as used in this application, may generally refer to the dimensional design value of a feature. Critical dimensions are of interest since they may represent the smallest dimension that may be formed on a semiconductor topography using various techniques such as photolithography and etch. Unfortunately, as the dimensions of advanced semiconductor devices are reduced, problems associated with forming contact openings having uniform critical dimensions across a wafer typically increase. For example, current etch processes may not form contact openings of uniform critical dimensions across a wafer. As such, the critical dimensions of the contact openings across the wafer may vary. Furthermore, the critical dimensions of contact openings may also vary from wafer to wafer.
Accordingly, it would be advantageous to develop a method for forming contact openings through a dielectric layer using a barrier layer of reduced thickness to protect underlying semiconductor or metal interconnect layers while forming contact openings of uniform critical dimension across the wafer.
The problems outlined above may be in large part addressed by a method for etching a dielectric layer formed upon a barrier layer with an etch chemistry including CxHyFz, in which xxe2x89xa72, yxe2x89xa72, and zxe2x89xa72. For example, CxHyFz may include C2H2F4, which may be commonly referred to as Freon 134 or F134. In addition, CxHyFz may also be a heavier fluorinated hydrocarbon such as C4H2F6. Such an etch chemistry may be selective to the barrier layer. The selectivity of an etch chemistry or etch process may be generally defined as the ratio of the etch rates of different materials which are being etched. For example, the etch chemistry may have a dielectric layer:barrier layer selectivity of at least approximately 20:1, but may range from approximately 20:1 to approximately 50:1. Therefore, etching a dielectric layer with such an etch chemistry may terminate upon exposing an upper surface of the barrier layer. As such, a thickness of a barrier layer used to protect an underlying layer may be reduced to, for example, approximately 100 angstroms to approximately 150 angstroms. In addition, critical dimensions of contact openings formed with such an etch chemistry may be substantially uniform across a wafer. Furthermore, contact openings formed with such an etch chemistry may have uniform critical dimensions from wafer to wafer.
According to an embodiment, a conductive layer may be formed upon a semiconductor layer. The semiconductor layer may be a semiconductor substrate such as a monocrystalline silicon semiconductor substrate. Alternatively, the semiconductor layer may include various structures on another level of a semiconductor device. The semiconductor layer may also include diffusion or isolation regions, which may be formed in the semiconductor layer. A conductive layer such as aluminum, copper, or polysilicon may be formed upon the semiconductor layer. A barrier layer, which may include a metal such as titanium or a metal alloy such as titanium nitride (TiN), titanium tungsten (TiW), tantalum (Ta), or tantalum nitride (TaN) may be formed upon the conductive layer. The barrier layer and the conductive layer may then be used to form a metallization layer or any number of gate structures or local interconnect structures on and laterally spaced across the semiconductor layer.
A layer of dielectric material may then be formed upon and in contact with the metallization layer or formed structures and the semiconductor layer. The dielectric layer may be an interlevel dielectric layer such that the dielectric layer may insulate conductive structures on multiple levels of a semiconductor topography. The dielectric layer may be a material sufficient to insulate laterally adjacent structures such as local interconnects or gate electrodes. For example, appropriate dielectric materials may include silicon dioxide (SiO2), tetraorthosilicate glass (TEOS), silicon nitride (SixNy), silicon oxynitride (SiOxNy(Hz)), or silicon dioxide/silicon nitride/silicon dioxide (ONO). The dielectrics may be deposited by physical deposition such as sputtering or by a variety of chemical deposition methods and chemistries such as chemical vapor deposition. Additionally, the dielectrics may be undoped or may be doped, for example, with boron, phosphorus, boron and phosphorus, or fluorine, to form a doped dielectric layer such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and fluorinated silicate glass (FSG).
The dielectric layer may be etched with an etch chemistry in regions of the dielectric layer which have been exposed by patterning an overlying etch mask layer. An etch chemistry may be flowed in the form of a gas such that a dry etch process may be utilized. In a dry etch process, a semiconductor topography may be exposed to a plasma formed by flowing gases of the etch chemistry to etch exposed portions of a dielectric layer. Etching the dielectric layer may involve removing the dielectric layer from an upper surface of the dielectric layer to a level which may be approximately coplanar with an upper surface of the barrier layer. As such, etching the dielectric layer may include exposing a surface of the barrier layer. In addition, etching the dielectric layer may terminate upon exposing an upper surface of the barrier layer. Etching the dielectric layer may be a timed process based on experimental data. Alternatively, etching the dielectric layer may involve stopping the etch process after an endpoint has been detected because etching the dielectric layer may involve removing the dielectric layer to the barrier layer. In this manner, an etched structure such as a contact opening may be formed from an upper surface of the dielectric layer to an upper surface of the barrier layer which may be used to form a contact structure.
The etch chemistry as described herein may include C2H2F4 and other halogenated compounds such as CF4, CHF3, C2F6, C4F8, C5F8, C4F6, SF6, and NF3. In addition, gases such as O2, Ar, N2, or He may be added to the etch chemistry. For example, an etch chemistry may include a combination of C2H2F4, CF4, and/or CHF3 as reactive etchant gases, and Ar and/or N2 as carrier/inert etchant gases for etching a dielectric layer. However, an appropriate etch chemistry may depend on, for example, the dielectric layer being etched, the stage of processing, the etch tool being used, the desired etch characteristics, such as etch rate and selectivity, and the desired properties of the feature being formed such as critical dimension and sidewall angle. Furthermore, a ratio of the etchant gases in an etch chemistry may be selected to optimize barrier layer selectivity and critical dimension uniformity. For example, an etch chemistry as described in the above embodiments may have a CxHyFz:(CF4, CHF3) ratio of approximately 2:3.5 to approximately 2:4. However, an appropriate CxHyFz:(CF4, CHF3) ratio may also vary depending on process conditions used for etching the dielectric layer.
A semiconductor device formed by the previously described method is also contemplated herein. The semiconductor device may include a barrier layer spaced above a semiconductor layer by a conductive layer. The barrier layer and the conductive layer may form gate structures, local interconnects, or a metallization layer. The barrier layer may have a thickness of approximately 70 angstroms to approximately 150 angstroms, or more preferably approximately 100 angstroms to approximately 150 angstroms. A dielectric layer may be formed upon and in contact with the barrier layer. In addition, a contact opening may be formed in the dielectric layer. The contact opening may be formed by etching the dielectric layer with an etch chemistry including C2H2F4. The contact opening may be filled with a conductive material to form a contact structure. Furthermore, interconnects may overlie the contact structure to connect to neighboring contact structures.
Etching a dielectric layer with an etch chemistry including CxHyFz, in which xxe2x89xa72, yxe2x89xa72, and zxe2x89xa72 may provide several advantages over standard methods for etching a dielectric layer. For example, an entire dielectric layer may be etched with the etch chemistry stopping on a barrier layer of reduced thickness without removing the barrier layer to expose the underlying layer. Because the etch chemistry may be significantly more selective to the barrier layer than to the dielectric layer, the etch chemistry may be used to rapidly etch an entire thickness of the dielectric layer. The etch chemistry, however, may etch the barrier layer at a significantly slower etch rate than the etch rate of the dielectric layer. Therefore, etching with the etch chemistry may be stopped before an entire barrier layer of reduced thickness has been removed such that the underlying layer may not be exposed to the etch chemistry. In this manner, a significant portion of the barrier layer may remain after etching the dielectric layer to protect the underlying layer. More specifically, the barrier layer may prevent the formation of undesirable compounds upon the upper surface of the underlying layer, thereby preventing an increase in resistance within conductive structures formed within the etched dielectric layer.
Consequently, the thickness of a barrier layer within a semiconductor device may be reduced to approximately 70 angstroms to approximately 150 angstroms, or more preferably approximately 100 angstroms to approximately 150 angstroms, in which the etch chemistry is used to etch a dielectric layer. In contrast, standard methods for etching a dielectric layer may typically require a barrier layer having a thickness of approximately 500 angstroms to approximately 1000 angstroms to protect the underlying layer. The formation of a barrier layer of reduced thickness may provide several advantages for the fabrication of a semiconductor device. For example, fabrication process time may be reduced. A barrier layer having a thickness of approximately 500 angstroms to approximately 1000 angstroms may take approximately 6 minutes to approximately 8 minutes to deposit. In contrast, a barrier layer of approximately 100 angstroms to approximately 150 angstroms may only require approximately 30 seconds to approximately 45 seconds to deposit. Therefore, reducing the thickness of a barrier layer may significantly reduce process time and may significantly increase production throughput and efficiency. Furthermore, barrier layer materials may typically be expensive and reducing a thickness of the barrier layer may provide a substantial reduction in the cost of fabricating a semiconductor device.
In addition, etching a dielectric layer with an etch chemistry including C2H2F4, may promote formation of a layer of a passivating polymer within the etched contact opening. Because etch processing conditions may be selected such that the etchant ions may reach the semiconductor substrate at a substantially perpendicular angle, the layer of passivating polymer may be sufficiently removed from bottom surface within the contact opening. In this manner, etching may not be prematurely stopped by polymer buildup within the contact opening. The sidewalls of the contact openings, however, may not be subjected to sufficient bombardment by the etchant ions such that the layer of polymer may not be removed. The layer of polymer may serve to further protect the sidewalls of the contact opening from etchant ions, which may be directed toward the sidewalls of the contact opening and which may cause the sidewall angle to deviate from a perpendicular angle. After termination of the etch process, polymer formed upon sidewall surfaces of the contact openings may be removed by using a wet etch process prior to any further processing. Therefore, although an initial thickness of a dielectric layer may vary across a wafer or from wafer to wafer, the lateral dimensions of contact opening may be substantially uniform from chip to chip on a wafer and from wafer to wafer. Consequently, using such an etch chemistry to etch a dielectric layer may be used to form semiconductor devices having substantially uniform critical dimensions.